1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device; and, more particularly, a method for forming a channel of a lateral double diffused MOSFET (LDMOS).
2. Description of Related Art
Recently, a modular system on chip (MSOC) including a modular bipolar complementary metal oxide semiconductor-discrete metal oxide semiconductor (MBCD) single integrated circuit has been used for an integrated circuit of a smart cards to embody telecommunication system for high frequency and high internal pressure such as automotive power integrated circuits and a direct current to direct current (DC/DC) converter with an increasing demand.
A lateral double diffused MOSFET (LDMOS) is mainly used in a Power Integrated Circuit (PIC) as an essential device of a bipolar CMOS DMOS (BCD) process. Since the LDMOS has high input impedance in comparison with a bipolar transistor, a power gain is large and a gate driver circuit is very simple. Also, since a device is a unipolar device, there is no time delay occurring due to accumulation or recombination by a few carrier during a turn-off time.
FIGS. 1A to 1C are cross-sectional views describing a conventional LDMOS fabricating method. Herein, a method for fabricating the LDMOS having an n-channel will be described as an example.
As shown in FIG. 1A, an n-well 102 is formed over a p-type semiconductor substrate 100 doped at a relatively high density. The n-well 102 functions as a drain region.
Subsequently, a field insulation layer 104 is formed over the semiconductor substrate 100. Subsequently, a photoresist pattern 106 is formed over the semiconductor substrate 100. Subsequently, an impurity region 108 is formed inside the semiconductor substrate 100 using the photoresist pattern 106 as a mask. At this time, impurities having different conductive types and diffusion forces are simultaneously implanted to realize a source region 110 and a channel region 112 of FIG. 1B in the impurity region 108 at the same time. For example, arsenic (As), which is a material of group V in a periodic table, for realizing the n-type source region 110 in the impurity region 108 and boron (B), which is a material of group III in the periodic table, for realizing the p-type channel region 112 are simultaneously implanted.
As shown in FIG. 1B, the boron (B) implanted in the impurity region 108 is diffused into the n-well 102 through a diffusion process. At this time, the arsenic (As) of a low diffusion level in comparison with the boron (B) is not diffused and remains in the impurity region 108. Only the boron (B) of the high diffusion level is diffused into the n-well 102. Accordingly, the arsenic (As) remains in the impurity region 108 to form the source region 110 and the channel region 112 is formed to enclose the source region 110 with the boron (B) diffused from the impurity region 108.
As shown in FIG. 1C, a gate electrode including a gate insulation layer 114 and a gate conductive layer 116 is formed over the semiconductor substrate 100. At this time, a part of the gate electrode is overlapped with the channel region 112.
However, following is a problem associated with the conventional LDMOS fabricating method.
As described in FIG. 1B, since the self-aligned channel region 112 is formed over the source region 110 by using a diffusion level difference between the impurities implanted in the impurity region 108 in the conventional technology, a profile of the channel region 112, i.e., a channel length, can be uniformly maintained. However, since the channel length is determined according to the diffusion process, a device is not realized by using the same process when the channel length is changed. A diffusion process time should be varied to change the channel length. At this time, a device characteristic such as threshold voltage or breakdown voltage may be changed.